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TK15321 Datasheet(PDF) 10 Page - TOKO, Inc |
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TK15321 Datasheet(HTML) 10 Page - TOKO, Inc |
10 / 12 page Page 10 May 1999 TOKO, Inc. TK15321 APPLICATION INFORMATION Figure 11 Figure 12 Figure 13 Figure 14 KEY INPUT CIRCUIT 1ch and 2ch is separate action by each control keys. Figure 11 is an equivalence circuit of key input. When terminal of key is the open, is outputting high level (about 1.4 V), and then Ach input signal is outputted. The channel at TK15321M can be changed by low level. When a control terminal was operated to low function, sometimes it may flow out maximum values about 30 µA as current from the terminal. For this reason, please use a resistance which does not exceed 0.8 V when attaching a resistance to the outside and making a low condition. SWITCHING TIME This time is the signal change response time compared to the control key input signal. Figure 12 illustrates the timimg chart. T = 2 µs typically. APPLICATION Figure 13 illustrates an example of a typical application. The standard application is to use capacitor coupling at the inputs and output of the TK15321M. For characteristics of distortion and dynamic range versus R L, refer to the graphs in the Typical Performance Characteristics. The TK15321M can also be used with direct coupling, but the characteris- tics will get worse (distortion, etc.). If direct coupling is desired, then it is recommended to use external circuitry that is biased compatible with the TK15321M. Input of the TK15321M is the open base type. CROSS TALK (ISOLATION AND SEPARATION) Figure 14 is an example of a layout pattern. In the application of the TK15321M, the following must be considered. Because of the high impedance at the inputs, the capacitors can act as antennas to each other. If the parts are bigger, and the space between the capacitors is too narrow, then cross talk will increase. Therefore, when designing the printed circuit pattern, separate the input capacitors as far as possible and use as small a part as possible (e.g., surface mount types, etc.). Key in to Logic i Key in Bch (Ach) SW out 50% Ach (Bch) t 1OUT 1BIN VCC GND 2BIN 2OUT 1AIN 1KEY 2KEY 2AIN + + 10 µF RL 10 µF 1Bin 11 10 9 8 7 + 10 µF + 2 Bin 1Key 2Key 10 µF + RL 10 µF + 10 µF + 33 µF 1Ain 2Ain |
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