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V•I Chip Voltage Transformation Module

V048F030T070

Rev. 2.7

Page 9 of 11

Figure 15 — VTM test circuit

Parallel Operation

In applications requiring higher current or redundancy, VTMs can be

operated in parallel without adding control circuitry or signal lines. To

maximize current sharing accuracy, it is imperative that the source and

load impedance on each VTM in a parallel array be equal. If VTMs are

being fed by an upstream PRM, the VC nodes of all VTMs must be

connected to the PRM VC.

To achieve matched impedances, dedicated power planes within the PC

board should be used for the output and output return paths to the

array of paralleled VTMs. This technique is preferable to using traces of

varying size and length.

The VTM power train and control architecture allow bi-directional

power transfer when the VTM is operating within its specified ranges.

Bi-directional power processing improves transient response in the

event of an output load dump. The VTM may operate in reverse,

returning output power back to the input source. It does so efficiently.

Input Impedance Recommendations

To take full advantage of the VTM’s capabilities, the impedance of the

source (input source plus the PC board impedance) must be low over a

range from DC to 5 MHz. The input of the VTM (factorized bus) should

be locally bypassed with a 8 µF low Q aluminum electrolytic capacitor.

Additional input capacitance may be added to improve transient

performance or compensate for high source impedance. The VTM has

extremely wide bandwidth so the source response to transients is

usually the limiting factor in overall output response of the VTM.

Anomalies in the response of the source will appear at the output of

the VTM, multiplied by its K factor of 1/16. The DC resistance of the

source should be kept as low as possible to minimize voltage deviations

on the input to the VTM. If the VTM is going to be operating close to

the high limit of its input range, make sure input voltage deviations will

not trigger the input overvoltage turn-off threshold.

Input Fuse Recommendations

V•I Chips are not internally fused in order to provide flexibility in

configuring power systems. However, input line fusing of V•I Chips

must always be incorporated within the power system. A fast acting

fuse is required to meet safety agency Conditions of Acceptability. The

input line fuse should be placed in series with the +In port.

Application Notes

For VTM and V•I Chip application notes on soldering, thermal

management, board layout, and system design click on the link below:

http://www.vicorpower.com/technical_library/application_information/chips/

Application Note

F1

Load

+

–

Input reflected ripple

measurement point

C2

0.47

μF

ceramic

+

–

14 V

-In

PC

VC

TM

+In

-Out

+Out

VTM

+Out

-Out

K

Ro

Notes:

C3 should be placed close

to the load

R3 may be ESR of C3 or a

separate damping resistor.

C3

10 µF

R3

10 mΩ

C1

47 µF

Al electrolytic

7A

Fuse

+

–

+

K

+

–

+

–

–

V•I Chip VTM Level 1 DC Behavioral Model for 48 V to 3 V, 70 A

Figure 16 — This model characterizes the DC operation of the V•I Chip VTM, including the converter transfer function and its losses. The model enables

estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.

©

1.7 mΩ

1/16 • Vin

1/16 • Iout

63 mA