1.5Msps, Single-Supply, Low-Power, True-

Differential, 12-Bit ADCs with Internal Reference

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9

Pin Description

PIN

NAME

FUNCTION

1

AIN-

Negative Analog Input

2

REF

Reference Voltage Output. Internal 2.048V reference output. Bypass REF with a 0.01µF capacitor and

a 4.7µF capacitor to RGND.

3

RGND

Reference Ground. Connect RGND to GND.

capacitor to GND.

5, 11

N.C.

No Connection

6

GND

Ground. GND is internally connected to EP.

to GND.

8

DOUT

Serial Data Output. Data is clocked out on the rising edge of SCLK.

9

CNVST

Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the

falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.

10

SCLK

Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.

12

AIN+

Positive Analog Input

—

EP

Exposed Paddle. EP is internally connected to GND.

Detailed Description

The MAX1277/MAX1279 use an input T/H and succes-

sive-approximation register (SAR) circuitry to convert

an analog input signal to a digital 12-bit output. The

serial interface requires only three digital lines (SCLK,

CNVST, and DOUT) and provides easy interfacing to

microprocessors (µPs) and DSPs. Figure 3 shows the

simplified internal structure for the MAX1277/MAX1279.

RGND

AIN +

GND

DOUT

SCLK

CNVST

CONTROL

LOGIC AND

TIMING

AIN -

REF

12-BIT

SAR

ADC

MAX1277

MAX1279

TRACK AND

HOLD

OUTPUT

BUFFER

REF

2.048V

Figure 3. Functional Diagram

AIN+

AIN-

CONTROL

LOGIC

CAPACITIVE

DAC

COMP

ACQUISITION MODE

AIN+

AIN-

CONTROL

LOGIC

CAPACITIVE

DAC

COMP

HOLD/CONVERSION MODE

Figure 4. Equivalent Input Circuit