Low-Jitter Frequency Synthesizer

with Selectable Input Reference

_______________________________________________________________________________________

9

Pin Description (continued)

PIN

NAME

FUNCTION

37

OUTA3

38

OUTA3

Clock Output A3, Differential LVPECL

39

OUTA2

40

OUTA2

Clock Output A2, Differential LVPECL

43

DA

Four-Level Control Input for A-Group Output Divider. See Table 2.

44

OUTA1

45

OUTA1

Clock Output A1, Differential LVPECL

46

OUTA0

47

OUTA0

Clock Output A0, Differential LVPECL

50

PLL_BYPASS

PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has

internal 90k

pulldown to GND. Connect high to bypass the PLL, connecting the selected

reference clock directly to the clock outputs. In this mode, the clock qualification function

is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled

by shorting the CREG pin to GND.

51

RSVD3

54

RSVD4

Reserved. Leave pin open.

55

LOCK

PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked.

56

IN1FAIL

REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock

qualification. Once a failed clock is detected, the indicator status is latched and updated

every 128 PFD cycles (~ 2μs).

—

EP

Exposed Pad. Connect to supply ground for proper electrical and thermal performance.

Detailed Description

The MAX3673 integrates two differential LVPECL refer-

ence inputs with a 2:1 mux, a PLL with configurable

dividers, nine differential LVPECL clock outputs, and a

selectable external feedback input for zero-delay buffer

applications (see the

Functional Diagram).

The two reference clock inputs are continuously moni-

tored for clock failure by the internal PLL and associat-

ed logic. If the primary clock fails, the user can switch

over to the secondary clock using the 2:1 mux.

The PLL accepts reference input frequencies of 61.44,

122.88, 245.76, or 307.2MHz and generates output fre-

quencies of 61.44, 122.88, 153.6, 245.76, or 307.2MHz.

The nine clock outputs are organized into two groups

(A and B). Each group has a configurable frequency

divider and output-enable control.

Phase-Locked Loop (PLL)

The PLL contains a phase-frequency detector (PFD),

charge pump (CP) with a lowpass filter, and voltage-

controlled oscillator (VCO). The PFD compares the

divided reference frequency to the divided VCO output

at 61.44MHz, and generates a control signal to keep

the VCO phase and frequency locked to the selected

reference clock. Using a high-frequency VCO

(2.457GHz) and low-loop bandwidth (40kHz), the

MAX3673 attenuates reference clock jitter while main-

taining lock and generates low-jitter clock outputs at

multiple frequencies. Typical jitter generation is

To minimize supply noise-induced jitter, the VCO sup-

ply (VCC_VCO) is isolated from the core logic and out-

put buffer supplies. Additionally, the MAX3673 uses an

internal low-dropout (LDO) regulator to attenuate noise

from the power supply. This allows the device to

achieve excellent power-supply noise rejection, signifi-

cantly reducing the impact on jitter generation.

Clock Failure Conditions

The MAX3673 clock failure detection is performed

using the combination of amplitude qualification and

PLL frequency and phase-error qualification. The failure

status is indicated for REFCLK0 and REFCLK1 at