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CS2300P-CZZ Datasheet(PDF) 1 Page - Cirrus Logic |
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CS2300P-CZZ Datasheet(HTML) 1 Page - Cirrus Logic |
1 / 26 page Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved) http://www.cirrus.com Fractional-N Clock Multiplier with Internal LCO Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 50 Hz to 30 MHz Clock Source Internal LCO Reference Clock Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in High- Resolution Mode One-Time Programmability – Configurable Hardware Control Pins – Configurable Auxiliary Output Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analog- digital PLL architecture comprised of a unique combina- tion of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 Hz. The CS2300-OTP has many configuration op- tions which are set once prior to runtime. At runtime there are three hardware configuration pins available for mode and feature selection. The CS2300-OTP is available in a 10-pin MSOP pack- age in Commercial (-10°C to +70°C) grade. Customer development kits are also available for custom device prototyping, small production programming, and device evaluation. Please see “Ordering Information” on page 25 for complete details. Auxiliary Output 6 to 75 MHz PLL Output Frequency Reference 3.3 V Fractional-N Frequency Synthesizer Digital PLL & Fractional N Logic Output to Input Clock Ratio N PLL Output Lock Indicator 50 Hz to 30 MHz Frequency Reference LCO Hardware Configuration Hardware Control AUG '09 DS844F1 CS2300-OTP |
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Similar Description - CS2300P-CZZ |
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