SRAM

SRAM

SRAM

SRAM

SRAM

AS8S128K32

AS8S128K32

Rev. 4.1 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

Austin Semiconductor, Inc.

7. At any given temperature and voltage condition,

t

8. ?W/E is HIGH for READ cycle.

9. Device is continuously selected. Chip enables and output

enable are held in their active state.

10. Address valid prior to or coincident with latest occurring

chip enable.

11. t

12. Chip enable (?C/E) and write enable (?W/E) can initiate and

terminate a WRITE cycle.

13. 32 bit operation

NOTES

1. All voltages referenced to V

2. -3v for pulse width <20ns.

The specified value applies with the outputs

4. This parameter is sampled.

5. Test conditions as specified with output loading as

shown in Fig. 1 unless otherwise noted.

6. t

as in Fig. 2. Transition is measured +/- 200 mV

typical from steady state coltage, allowing for actual

tester RC time constant.

open, and f=

1

LOW V

tR

tCDR

DATA RETENTION MODE

DATA RETENTION MODE

VDR

VDR

Vcc

CE\

4.5V

4.5V

>2V

V

IH

V

IL

DATA RETENTION ELECTRICAL CHARACTERISTICS

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

NOTES

2--

V

--

6

mA

--

11.6

mA

Chip Deselect to Data

Retention Time

0--

ns

4

Operation Recovery Time

ns

4, 11

Data Retention Current

CONDITIONS