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AS1419A Datasheet(PDF) 7 Page - Austin Semiconductor |
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AS1419A Datasheet(HTML) 7 Page - Austin Semiconductor |
7 / 20 page ADC ADC ADC ADC ADC AS1419 AS1419A AS1419 & AS1419A Rev. 1.5 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 Austin Semiconductor, Inc. TYPICAL PERFORMANCE CHARACTERISTICS (cont.) TEST CIRCUITS Load Circuit for Access timings Load Circuits for Output Float Delay PIN FUNCTIONS +AIN (Pin 1): ±2.5V Positive Analog Input. –AIN (Pin 2): ±2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1µF. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 10 μF tantalum in parallel with 0.1µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The output format is 2’s complement. DGND (Pin 14): Digital Ground for Internal Logic. Tie toAGND. D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The output format is 2’s complement. SHDN\ (Pin 21): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS\. CS\ = 0 for nap mode and CS\ = 1 for sleep mode. RD\ (Pin 22): Read Input. This enables the output drivers when CS\ is low. CONVST\ (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS\ (Pin 24): Chip Select. The input must be low for the ADC to recognize CONVST\ and RD\ inputs. CS\ also sets the shutdown mode when SHDN\ goes low. CS\ and SHDN\ low select the quick wake-up nap mode. CS\ high and SHDN\ low select sleep mode. BUSY\ (Pin 25): The BUSY\ output shows the converter status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY\. V SS (Pin 26): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. DV DD (Pin 27): 5V Positive Supply. Short to Pin 28. AV DD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. |
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