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SM55161A-70HKCI Datasheet(PDF) 7 Page - Austin Semiconductor |
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SM55161A-70HKCI Datasheet(HTML) 7 Page - Austin Semiconductor |
7 / 64 page VRAM SM55161A Production Austin Semiconductor, Inc. AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice. 7 SMJ55161A Rev. 1.6 03/05 output enable/transfer select (TRG\) TRG\ selects either DRAM or transfer operation as RAS\ falls. For DRAM operation, TRG\ must be held high as RAS\ falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0–DQ15. For transfer operation, TRG\ must be brought low before RAS\ falls. write-mask select, write enable (WE) In DRAM operation, WE\ enables data to be written to the DRAM. WE\ is also used to select the DRAM write-per-bit mode. Holding WE\ low on the falling edge of RAS\ invokes the write-per-bit operation. The SMJ55161A supports both the nonpersistent write-per-bit mode and the persistent write-per- bit mode. special-function select (DSF) The DSF input is latched on the falling edge of RAS\ or the first falling edge of CASx\, similar to an address. DSF deter- mines which of the following functions are invoked on a par- ticular cycle: • CBR refresh with reset (CBR) • CBR refresh with no reset (CBRN) • CBR refresh with no reset and stop-point set (CBRS) • Block write • Loading write-mask register for the persistent write-per-bit mode (LMR) • Loading color register for the block-write mode • Split-register-transfer read DRAM data I/O, write mask data (DQ0–DQ15) DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG\ is brought low. Data appears at the outputs until TRG\ returns high, CASx\ returns high following RAS\ returning high, or RAS\ returns high following CASx\ returning high. The write mask is latched into the device through the random DQ pins by the falling edge of RAS\ and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. serial-data outputs (SQ0 –SQ15) Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long as the serial-enable pin, SE\, is high. The serial outputs are enabled when SE\ is brought low. serial clock (SC) Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161A is designed to work with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC- clock operating frequency. serial enable (SE) During serial-access operations, SE\ is used as an enable/ disable for the SQ outputs. SE\ low enables the serial-data out- put while SE\ high disables the serial-data output. SE\ is also used as an enable/disable for output pin QSF. IMPORTANT: While SE\ is held high, the serial clock is not disabled. External SC pulses increment the internal serial- address counter regardless of the state of SE\. This ungated serial-clock scheme minimizes access time of serial output from SE\ low because the serial-clock input buffer and the serial- address counter are not disabled by SE\. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of the serial register (SAM). When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. During full-register-transfer operations, QSF can change state upon completing the cycle. This state is determined by the tap point loaded during the transfer cycle. QSF is enabled by SE\; therefore, if SE\ is high, the QSF output is in the high- impedance state. no connect / ground (NC/GND) NC/GND must be tied to system ground or left floating for proper device operation. |
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