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ADIS16260BCCZ Datasheet(PDF) 5 Page - Analog Devices |
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ADIS16260BCCZ Datasheet(HTML) 5 Page - Analog Devices |
5 / 19 page Preliminary Technical Data ADIS16260/ADIS16265 Rev. PrB | Page 5 of 19 TIMING SPECIFICATIONS TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted. Table 2. Parameter Description Min1 Typ Max1 Unit fSCLK Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) 0.01 2.5 MHz Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) 0.01 1.0 MHz tDATARATE Data rate period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) 32 μs Data rate period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) 42 μs tSTALL Stall period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) 9 μs Stall period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) 12 μs tCS Chip select to clock edge 48.8 ns tDAV Data output valid after SCLK falling edge2 100 ns tDSU Data input setup time before SCLK rising edge 24.4 ns tDHD Data input hold time after SCLK rising edge 48.8 ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSFS CS high after SCLK edge3 5 ns Flash update time (power supply must be within range) 50 ms 1 Guaranteed by design; not production tested. 2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state. CS SCLK tDATARATE tDATASTALL Figure 2. SPI Chip Select Timing CS SCLK DOUT DIN 1 2 3 4 5 6 15 16 W/R A5 A4 A3 A2 D2 MSB DB14 D1 LSB DB13 DB12 DB10 DB11 DB2 LSB DB1 tCS tSFS tDAV tDHD tDSU * *NOT DEFINED Figure 3. SPI Timing (Using SPI Settings Typically Identified as Phase = 1, Polarity = 1) |
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