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FIN210AC Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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FIN210AC Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 17 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN210AC • Rev. 1.0.1 5 Table 3. Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values) LVCMOS Output Edge Rates S0 S1 Slow Edge Rates ~7 - 8ns (CL = 8pF) 0 1 Medium Edge Rates ~4 - 5ns (CL = 8pF) 1 1 Fast Edge Rates ~2 - 3ns (CL = 8pF) 1 0 Power Down 0 0 Pulse Width Calculations CKP Pulse Width Low Time=(PLL Multiplier • Pwidth Multiplier) / (CKREF•12) (1) Example: CKREF=26MHz ; PLL Multiplier=1; Pwidth Multiplier=6 CKP Pulse width=(1 • 6) / (26MHz • 12)=19.2ns (2) CKREF = Strobe 50% Duty Cycle If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP Table 4. CKREF = Strobe 50% Duty Cycle Serializer Deserializer PLL0 PLL1 PWS0 PWS1 1 0 0 0 Power-Down States When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode. Table 5. Power-Down Signal Pins DIRI=1 (Serializer) DIRI=0 (Deserializer) /ENZ = 0 DIRI=0 (Deserializer) /ENZ = 1 DP[1:10] Inputs Disabled Outputs High-Z Outputs Low CKP HIGH High-Z High STROBE Input Disabled Input Disabled Input Disabled CKREF Input Disabled Input Disabled Input Disabled /DIRO 0 1 1 |
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Similar Description - FIN210AC |
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