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CHR3694-QDG Datasheet(PDF) 15 Page - United Monolithic Semiconductors |
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CHR3694-QDG Datasheet(HTML) 15 Page - United Monolithic Semiconductors |
15 / 18 page 37-40GHz Down Converter CHR3694-QDG Ref. : DSCHR3694-QDG – February 09 15/18 Specifications subject to change without notice Route Départementale 128, BP46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0) 1 69 33 03 08 - Fax: +33 (0) 1 69 33 03 09 Notes The biasing circuits of the stages of the circuit are given in the schemes below. Vd=4V Stage 1 Stage 2 Stage 3 150 Ω Vgc=-2V 0V Self-biased Self-biased Gain control Self-biased 1.9k Ω 1.9k Ω 26 Ω 100 Ω 26 Ω 100 Ω 60 Ω 60 Ω 1.9k Ω 9 Ω 100 Ω 21 Ω IN OUT LNA Vd=4V Stage 1 Stage 2 Stage 3 150 Ω Vgc=-2V 0V Self-biased Self-biased Gain control Self-biased 1.9k Ω 1.9k Ω 26 Ω 100 Ω 26 Ω 100 Ω 60 Ω 60 Ω 1.9k Ω 9 Ω 100 Ω 21 Ω IN OUT LNA Vdx=4V Stage Buffer 1 Stage 2 times multiplier Stage Buffer 2 Vgx Self-biased Self-biased 1.23k Ω 10 Ω 42 Ω 200 Ω 38 Ω 1.23k Ω 8 Ω 57 Ω LO IN LO OUT LO Vdx=4V Stage Buffer 1 Stage 2 times multiplier Stage Buffer 2 Vgx Self-biased Self-biased 1.23k Ω 10 Ω 42 Ω 200 Ω 38 Ω 1.23k Ω 8 Ω 57 Ω LO IN LO OUT LO Vgm 1.2k Ω 0.5 Ω 0.5 Ω Vgm 1.2k Ω 0.5 Ω 0.5 Ω |
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