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M13S64322A Datasheet(PDF) 2 Page - Elite Semiconductor Memory Technology Inc. |
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M13S64322A Datasheet(HTML) 2 Page - Elite Semiconductor Memory Technology Inc. |
2 / 49 page ESMT Preliminary M13S64322A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 0.5 2/49 DDR SDRAM 512K x 32 Bit x 4 Banks Double Data Rate Synchronous DRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bidirectional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 3, 4 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE DM0~DM3 for write masking only VDD = 2.5V ± 5%, VDDQ = 2.5V ± 5% Auto & Self refresh 15.6us refresh interval (2K / 32ms refresh) 1 DQS for QFP (4 DQS for FBGA) SSTL-2 I/O interface 100pin LQFP or QFP package (optional FBGA package, 144 balls, 0.5mm ball size, 0.8mm pitch) Operating Frequencies: Maximum Operating Frequency CAS Latency -4 -5 3 250MHz 200MHz |
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