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M13S128168A-4BG Datasheet(PDF) 8 Page - Elite Semiconductor Memory Technology Inc. |
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M13S128168A-4BG Datasheet(HTML) 8 Page - Elite Semiconductor Memory Technology Inc. |
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8 / 49 page  ESMT M13S128168A Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2008 Revision : 2.2 8/49 Command Truth Table COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP A11, A9~A0 Note Register Extended MRS H X L L L L X OP CODE 1,2 Register Mode Register Set H X L L L L X OP CODE 1,2 Auto Refresh H 3 Entry H L L L L H X X 3 L H H H 3 Refresh Self Refresh Exit L H H X X X XX 3 Bank Active & Row Addr. H X L L H H X V Row Address Auto Precharge Disable L 4 Read & Column Address Auto Precharge Enable H X L H L H X V H Column Address 4 Auto Precharge Disable L 4 Write & Column Address Auto Precharge Enable H X L H L L X V H Column Address 4,6 Burst Stop H X L H H L X X 7 Bank Selection V L Precharge All Banks H X L L H L X X H X 5 H X X X Entry H L L V V V X Active Power Down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge Power Down Mode Exit L H L V V V X X DM H X V X 8 H X X X No Operation Command H X L H H H XX (V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) 1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 1 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”.. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1: Bank select addresses. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected. If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. 5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). |
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