ESMT

M13S2561616A

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2009

Revision : 2.0

10/49

Mode Register Definition

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety

of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS

setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0

(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of

address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock

cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is

divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read

latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal

MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.

BA1 BA0 A12 A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Address Bus

0

0

0

0

0

0

DLL

TM

CAS Latency

BT

Burst Length

Mode Register

A8

DLL Reset

A7

Mode

A3

Burst Type

0

No

0

Normal

0

Sequential

1

Yes

1

Test

1

Interleave

Burst Length

CAS Latency

Latency

A6

A5

A4

Latency

A2

A1

A0

Sequential Interleave

BA1 BA0

Operating Mode

0

0

0

Reserve

0

0

0

Reserve

Reserve

0

0

MRS Cycle

0

0

1

Reserve

0

0

1

2

2

0

1

EMRS Cycle

0

1

0

2

0

1

0

4

4

0

1

1

3

0

1

1

8

8

1

0

0

Reserve

1

0

0

Reserve

Reserve

1

0

1

Reserve

1

0

1

Reserve

Reserve

1

1

0

2.5

1

1

0

Reserve

Reserve

1

1

1

Reserve

1

1

1

Reserve

Reserve