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24C01C-I/ST Datasheet(PDF) 6 Page - Microchip Technology

Part No. 24C01C-I/ST
Description  1K 5.0V I2C™ Serial EEPROM
Download  30 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

24C01C-I/ST Datasheet(HTML) 6 Page - Microchip Technology

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DS21201J-page 6
© 2008 Microchip Technology Inc.
The 24C01C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access, and generates the Start
and Stop conditions, while the 24C01C works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Bus Not Busy (A)
Both data and clock lines remain high.
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out fashion.
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the
master to generate the Stop condition (Figure 4-2)
The 24C01C does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.

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