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STM32W108CBU64 Datasheet(PDF) 73 Page - STMicroelectronics |
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STM32W108CBU64 Datasheet(HTML) 73 Page - STMicroelectronics |
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73 / 179 page  STM32W108CB, STM32W108HB Serial interfaces Doc ID 16252 Rev 2 73/179 7.7.2 Serial DMA status register (SCx_DMASTAT) Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT) Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_TX DMARS T SC_R XDMA RST SC_TX LODB SC_TX LODA SC_RX LODB SC_RX LODA rw rw rw rw rw rw rw rw rw rw w w rw rw rw rw [5] SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears automatically. [4] SC_RXDMARST: Setting this bit resets the receive DMA. The bit clears automatically. [3] SC_TXLODB: Setting this bit loads DMA transmit buffer B addresses and allows the DMA controller to start processing transmit buffer B. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. [2] SC_TXLODA: Setting this bit loads DMA transmit buffer A addresses and allows the DMA controller to start processing transmit buffer A. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. [1] SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. [0] SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the DMA controller to start processing receive buffer A. If both buffer A and B are loaded simultaneously, buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has no effect. Reading this bit returns DMA buffer status: 0: DMA processing is complete or idle. 1: DMA processing is active or pending. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw |
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