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PA04 Datasheet(PDF) 4 Page - Cirrus Logic |
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PA04 Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 5 page P r o d u c t I n n o v a t i o n F r o m PA04 • PA04A 4 PA04U GENERAL Please read Application Note 1 "General Operating Con- siderations" which covers stability, supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selection; Apex Precision Power’s completeApplication Notes library;Technical Seminar Workbook; and Evaluation Kits. CURRENTLIMIT The two current limit sense lines are to be connected directly across the current limit sense resistor. For the current limit to work correctly pin 11 must be connected to the amplifier output side and pin 10 connected to the load side of the current limit resistor, R CL, as shown in Figure 1. This connection will bypass any parasitic resistances, Rp, formed by sockets and solder joints as well as internal amplifier losses. The current limiting resistor may not be placed anywhere in the output circuit except where shown in Figure 1. The value of the current limit resistor can be calculated as follows: .76 R CL = I LIMIT Figure 1. Current Limit. SAFEOPERATINGAREA(SOA) The MOSFET output stage of this power operational ampli- fier has two distinct limitations: 1. The current handling capability of the MOSFET geometry and the wire bonds. 2. The junction temperature of the output MOSFETs. NOTE: The output stage is protected against transient fly- back. However, for protection against sustained, high energy flyback, external fast-recovery diodes should be used. SLEEPMODEOPERATION In the sleep mode, pin 12 (sleep) is tied to pin 9 (+V BOOST). This disables the amplifier’s internal reference and the am- plifier shuts down except for a trickle current of 3 mA which flows into pin 12. Pin 12 should be left open if the sleep mode is not required. Several possible circuits can be built to take advantage of this mode. In Figure 2A a small signal relay is driven by a logic gate. This removes the requirement to deal with the common mode voltage that exists on the shutoff circuitry since the sleep mode is referenced to the +V BOOST voltage. In Figure 2B, circuitry is used to level translate the sleep mode input signal. The differential input activates sleep mode with a differential logic level signal and allows common mode voltages to ±V BOOST. BOOSTOPERATION With the V BOOST feature the small signal stages of the amplifier are operated at higher supply voltages than the amplifier’s high current output stage. +V BOOST (pin 9) and –V BOOST (pin 5) are connected to the small signal circuitry of the amplifier. +V S (pin 8) and –VS (pin 6) are connected to the high current output stage. An additional 5V on the V BOOST pins is sufficient to allow the small signal stages to drive the output transistors into saturation and improve the output voltage swing for extra efficient operation when required. When close swings to the supply rails is not required the +V BOOST and +VS pins must be strapped together as well as the –V BOOST and –VS pins. The boost voltage pins must not be at a voltage lower than the V S pins. COMPENSATION The external compensation components C C and RC are con- nected to pins 3 and 4. Unity gain stability can be achieved at any compensation capacitance greater than 330 pF with at least 60 degrees of phase margin.At higher gains more phase shift can be tolerated in most designs and the compensation capacitance can accordingly be reduced, resulting in higher bandwidth and slew rate. Use the typical operating curves as a guide to select C C and RC for the application. FIGURE 2A. SLEEP MODE CIRCUIT. LOGIC K1 9 12 9 12 +V BOOST SLEEP +V BOOST SLEEP 560Ω 470Ω Q1 1KΩ Q2 –V BOOST 470Ω LOGIC INPUT + - FIGURE 2B. SLEEP MODE CIRCUIT. R f Ri 1 2 10 11 R CL PA04 R P R L CL CL INPUT 7 SOA 5.0 2.0 .5 .2 2 SUPPLY TO OUTPUT DIFFERENTIAL (V) 5 10 20 50 200 20 DC T C = 125°C DC T C = 85°C DC T C = 25°C t = 10ms t = 1ms 10 100 1.0 |
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