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PCA9555DB Datasheet(PDF) 11 Page - NXP Semiconductors |
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PCA9555DB Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 34 page PCA9555_8 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 08 — 22 October 2009 11 of 34 NXP Semiconductors PCA9555 16-bit I2C-bus and SMBus I/O port with interrupt 6.5.2 Reading the port registers In order to read data from the PCA9555, the bus master must first send the PCA9555 address with the least significant bit set to a logic 0 (see Figure 8 “PCA9555 device address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9555 (see Figure 12, Figure 13 and Figure 14). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. Remark: Transfer can be stopped at any time by a STOP condition. Fig 12. Read from register A S START condition R/W acknowledge from slave 002aac222 A acknowledge from slave SDA A P acknowledge from master DATA (first byte) slave address STOP condition S (repeated) START condition (cont.) (cont.) 1 0 0 A2 A1 A0 1 A 0 R/W acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter NA no acknowledge from master COMMAND BYTE 1 0 0 A2 A1 A0 0 0 data from lower or upper byte of register LSB MSB DATA (last byte) data from upper or lower byte of register LSB MSB |
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