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PPC5643LF0MLQ1R Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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PPC5643LF0MLQ1R Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 98 page Overview MPC5643L Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3 1 Overview This document provides electrical specifications, pin assignments, and package diagrams for the MPC5643L series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5643L Microcontroller Reference Manual. For use of the MPC5643Lin a fail-safe system according to safety standard IEC 61508, refer to the MPC5643LSafety Application Guide. The MPC5643L series microcontrollers are system-on-chip devices that are built on Power ArchitectureTM technology and: • Are 100% user-mode compatible with the classic Power Architecture instruction set • Contain enhancements that improve the architecture’s fit in embedded applications • Include additional instruction support for digital signal processing (DSP) • Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. The MPC5643L family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5643L automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original PowerPC user instruction set architecture (UISA). It operates at speeds as high as 120 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.1 Device comparison Table 1. MPC5643L device summary Feature MPC5643L CPU Type 2 × e200z4 (in lock-step or decoupled operation) Architecture Harvard Execution speed 0 – 120 MHz (+2% FM) DMIPS intrinsic performance > 240 MIPS SIMD (DSP + FPU) Yes MMU 16 entry Instruction set PPC Yes Instruction set VLE Yes Instruction cache 4 KB, EDC MPU-16 regions Yes, replicated module Semaphore unit (SEMA4) Yes Buses Core bus AHB, 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data Crossbar Master × slave ports Lock Step Mode: 4 × 3 Decoupled Parallel Mode: 6 × 3 |
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