AD9231BCPZRL7-40 datasheet(8/36 Pages) AD

Part #	AD9231BCPZRL7-40

Description	12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

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AD9231

Rev. 0 | Page 8 of 36

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

tSSYNC

SYNC to rising edge of CLK setup time

0.24

ns

tHSYNC

SYNC to rising edge of CLK hold time

0.40

ns

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

2

ns

tDH

Hold time between the data and the rising edge of SCLK

2

ns

tCLK

Period of the SCLK

40

ns

tS

Setup time between CSB and SCLK

2

ns

tH

Hold time between CSB and SCLK

2

ns

tHIGH

SCLK pulse width high

10

ns

tLOW

SCLK pulse width low

10

ns

tEN_SDIO

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

10

ns

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

10

ns

SYNC

CLK+

tSSYNC

tHSYNC

Figure 4. SYNC Input Timing Requirements

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AD9231BCPZRL7-40 Datasheet(PDF) 8 Page - Analog Devices

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