ADG1438/ADG1439

Rev. 0 | Page 11 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

1

2

3

4

5

6

7

8

9

10

DIN

GND

S2

S1

NC

SCLK

D

S4

S3

20

19

18

17

16

15

14

13

12

11

SDO

RESET

S6

S5

NC

S8

S7

SYNC

ADG1438

TOP VIEW

(Not to Scale)

Figure 5. ADG1438 Pin Configuration (TSSOP)

PIN 1

INDICATOR

NOTES

1. NC = NO CONNECT.

1

DIN

2

GND

3

S1

4

S2

5

S3

13 S5

15 RESET

12 S6

11 S7

TOP VIEW

(Not to Scale)

ADG1438

Figure 6. ADG1438 Pin Configuration (LFCSP)

Table 10. ADG1438 Pin Function Descriptions

Pin No.

TSSOP

LFCSP

Mnemonic

Description

1

19

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial

clock input. Data can be transferred at rates of up to 50 MHz.

2

20

Most Positive Power Supply Potential.

3

1

DIN

Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the

falling edge of the serial clock input.

4

2

GND

Ground (0 V) Reference.

5

7

NC

No Connect.

6

3

S1

Source Terminal 1. Can be an input or an output.

7

4

S2

Source Terminal 2. Can be an input or an output.

8

5

S3

Source Terminal 3. Can be an input or an output.

9

6

S4

Source Terminal 4. Can be an input or an output.

10

8

D

Drain Terminal. Can be an input or an output.

11

9

NC

No Connect.

12

10

S8

Source Terminal 8. Can be an input or an output.

13

11

S7

Source Terminal 7. Can be an input or an output.

14

12

S6

Source Terminal 6. Can be an input or an output.

15

13

S5

Source Terminal 5. Can be an input or an output.

16

14

Most Negative Power Supply Potential. In single-supply applications, it can be connected

to ground.

17

15

RESET

Active Low Logic Input. When this pin is low, all switches are open, and the appropriate registers

are cleared to 0.

18

16

SDO

Serial Data Output. Can be used for daisy-chaining a number of these devices together or for

reading back the data in the shift register for diagnostic purposes. The serial data is transferred on

the rising edge of SCLK and is valid on the falling edge of the clock. This is an open-drain output

19

17

Logic Power Supply Input. Operates from 2.7 V to 5.5 V.

20

18

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC

goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is

transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch

condition.

EPAD