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IS24C128-3GI Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS24C128-3GI Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
4 / 16 page 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. C 05/08/07 IS24C128 DEVICE OPERATION The IS24C128 features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUS The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by Master device which generates the SCL, controls the bus access and generates the Stop and Start conditions. The IS24C128 is the Slave device on the bus. The Bus Protocol: – Data transfer may be initiated only when the bus is not busy – During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. The state of the data line represents valid data after a Start condition. The data line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The IS24C128 monitors the SDA and SCL lines and will not respond until the Start condition is met. Stop Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. Acknowledge (ACK) After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. Reset The IS24C128 contains a reset function in case the 2- wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.) Standby Mode Power consumption in reduced in standby mode. The IS24C128 will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if no write operation is initiated; or c) Following any internal write operation DEVICE ADDRESSING The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave (Fig. 5) address is 8 bits. The four most significant bits of the address are fixed as 1010 for the IS24C128. This device has two address bits (A1 and A0), which allows up to four IS24C128 devices to share the 2-wire bus. Upon receiving the Slave address, the device compares the two address bits with the hardwired A1 and A0 input pins to determine if it is the appropriate Slave. If the A1 and A0 pins are not biased to High nor Low, then internal circuitry defaults the value to Low. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS24C128) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected IS24C128 then prepares for a Read or Write operation by monitoring the bus. WRITE OPERATION Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/ W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends two byte addresses that are to be written into the address pointer of the IS24C128. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24C128 acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device. |
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