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IS42S16400E-6TLI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc

Part # IS42S16400E-6TLI
Description  1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS42S16400E-6TLI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. C
08/07/09
IS42S16400E
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
FEATURES
• Clockfrequency:166,143MHz
• Fullysynchronous;allsignalsreferencedtoa
positive clock edge
• Internalbankforhidingrowaccess/precharge
• Single3.3Vpowersupply
• LVTTLinterface
• Programmableburstlength
–(1,2,4,8,fullpage)
• Programmableburstsequence:
Sequential/Interleave
• Selfrefreshmodes
• 4096refreshcyclesevery64ms
• Randomcolumnaddresseveryclockcycle
• ProgrammableCASlatency(2,3clocks)
• Burstread/writeandburstread/singlewrite
operations capability
• Burstterminationbyburststopandprecharge
command
• BytecontrolledbyLDQMandUDQM
• Package:400-mil54-pinTSOPII
• Lead-freepackageisavailable
• AvailableinIndustrialtemperature
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S16400E is
organizedas1,048,576bitsx16-bitx4-bankforimproved
performance.ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
AUGUST 2009
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ15
GNDQ
DQ14
DQ13
VDDQ
DQ12
DQ11
GNDQ
DQ10
DQ9
VDDQ
DQ8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
AddressInput
BA0,BA1
BankSelectAddress
DQ0toDQ15
DataI/O
CLK
SystemClockInput
CKE
ClockEnable
CS
Chip Select
RAS
RowAddressStrobeCommand
CAS
Column Address Strobe Command
WE
WriteEnable
LDQM
LowerBye,Input/OutputMask
UDQM
UpperBye,Input/OutputMask
VDD
Power
GND
Ground
VDDq
PowerSupplyforDQPin
GNDq
GroundforDQPin
NC
No Connection


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