IS42S16320B-75ETL datasheet(2/61 Pages) ISSI

Part #	IS42S16320B-75ETL

Description	64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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2

Integrated Silicon Solution, Inc. — www.issi.com

Rev. C

08/27/09

IS42S86400B, IS42/45S16320B

DEVICE OVERVIEW

The 512Mb SDRAM is a high speed CMOS, dynamic

random-accessmemorydesignedtooperatein3.3VVdd

and3.3VVddq memorysystemscontaining536,870,912

bits.Internallyconfiguredasaquad-bankDRAMwitha

synchronousinterface.Each134,217,728-bitbankisor-

ganizedas8,192rowsby1024columnsby16bits.Each

ofthex8's134,217,728-bitbanksisorganizedas8,192

rowsby2048columnsby8bits.

The512MbSDRAMincludesanAUTOREFRESHMODE,

and a power-saving, power-down mode. All signals are

registeredonthepositiveedgeoftheclocksignal,CLK.

AllinputsandoutputsareLVTTLcompatible.

The512MbSDRAMhastheabilitytosynchronouslyburst

data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks

to hide precharge time and the capability to randomly

change column addresses on each clock cycle during

burst access.

A self-timed row precharge initiated at the end of the burst

sequenceisavailablewiththeAUTOPRECHARGEfunction

enabled. Precharge one bank while accessing one of the

other three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

SDRAM read and write accesses are burst oriented starting

at a selected location and continuing for a programmed

number of locations in a programmed sequence.The

registration of an ACTIVE command begins accesses,

followedbyaREADorWRITEcommand.TheACTIVE

command in conjunction with address bits registered are

usedtoselectthebankandrowtobeaccessed(BA0,

BA1selectthebank;A0-A12selecttherow).TheREAD

or WRITE commands in conjunction with address bits

registered are used to select the starting column location

for the burst access.

ProgrammableREADorWRITEburstlengthsconsistof

1,2,4and8locationsorfullpage,withaburstterminate

option.

CLK

CKE

CS

RAS

CAS

WE

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

BA0

BA1

A10

A12

COMMAND

DECODER

&

CLOCK

GENERATOR

MODE

REGISTER

REFRESH

CONTROLLER

REFRESH

COUNTER

SELF

REFRESH

CONTROLLER

ROW

ADDRESS

LATCH

COLUMN

ADDRESSLATCH

BURSTCOUNTER

COLUMN

ADDRESSBUFFER

COLUMNDECODER

DATAIN

BUFFER

DATAOUT

BUFFER

DQML

DQMH

DQ0-15

VDD/VDDQ

Vss/VssQ

13

10

13

10

16

1024

(x16)

8192

MEMORYCELL

ARRAY

BANK 0

SENSEAMPI/OGATE

BANKCONTROLLOGIC

ROW

ADDRESS

BUFFER

A11

2

FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN)

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IS42S16320B-75ETL Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc

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