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IS64C5128AS Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS64C5128AS Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
10 / 19 page 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 03/04/2008 IS61C5128AL/AS IS64C5128AL/AS AC WAVEFORMS WRITE CYCLE NO. 1 ( WE WE WE WE WE Controlled)(1,2) DATA UNDEFINED t WC VALID ADDRESS t SCS t PWE1 t PWE2 t AW t HA HIGH-Z t HD t SA t HZWE ADDRESS CE WE DOUT DIN DATAIN VALID t LZWE t SD CE_WR1.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. |
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