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IS61DDB24M18-300M3L Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc

Part # IS61DDB24M18-300M3L
Description  72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS61DDB24M18-300M3L Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc.
Rev. B
11/10/09
72 Mb (2M x 36 & 4M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
Application Example
SA
LD R/W BW0 BW1 C C K K
DQ0–17
ZQ
SRAM #4
R=250
Vt
Data-In/Data-Out
Address
LD
R/W
BW
Memory
Controller
Return CLK
Source CLK
Return CLK
Source CLK
SA LD R/W BW0 BW1 C C K K
DQ0–17
ZQ
SRAM #1
R=250
Vt
R
Vt
Vt
R=50 Vt=VREF
R
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.


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