Integrated Silicon Solution, Inc.

7

Rev. B

11/10/09

72 Mb (2M x 36 & 4M x 18)

DDR-II (Burst of 2) CIO Synchronous SRAMs

The Timing Reference Diagram for Truth Table on page

8 is helpful in understanding the clock and write truth

tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read

and write commands are issued at the beginning of cycle “t”.

State Diagram

Linear Burst Sequence Table

Burst Sequence

Case 1

Case 2

First Address

01

Second Address

10

Power Up

DDR

-II Write

NOP

DDR

-II Read

Write

Write

Notes: 1. Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.

2. Read refers to read active status with R/W = high.

4. Load refers to read new address active status with LD = low.

3. Write refers to write active status with R/W = low.

Load New Address

Load

Load

Read

Load

Load

Load

Load

5. Load is read new address inactive status with LD = high.