Integrated Silicon Solution, Inc.

5

Rev. A

05/14/09

72 Mb (2M x 36 & 4M x 18)

DDR-II (Burst of 4) CIO Synchronous SRAMs

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the

burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the

second write burst address follows next, registered by the rising edge of K. The third data-out is clocked by

the subsequent rising edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of

the K clock.

The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into

the array on the third write cycle. A read cycle to the last two write address produces data from the write

buffers. The SRAM maintains data coherency.

During a write, the byte writes independently control which byte of any of the four burst addresses is written

(see X18/X36 Write Truth Tables on page

9, 10 and Timing Reference Diagram for Truth Table on page 8).

Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance

driven by the SRAM. For example, an RQ of 250

Ω results in a driver impedance of 50Ω. The allowable range

of RQ to guarantee impedance matching is between 175

Ω and 350Ω, with the tolerance described in

Programmable Impedance Output Driver DC Electrical Characteristics on page 1

4. The RQ resistor should

be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded

ZQ trace must be less than 3 pF.

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by

drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable

impedances values. The final impedance value is achieved within 1024 clock cycles.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C are both connected high at

power-up and must never change. Under this condition, K and K control the output timings.

ential clocks.

Depth Expansion

The following figure depicts an implementation of four

4M x 18 DDR-II SRAMs with common I/Os. In this appli-

cation example, the second pair of C and C clocks is delayed such that the return data meets the data setup

and hold times at the

memory controller.