Layout Considerations

The inputs and outputs are critical paths for the

MAX3624A, and care should be taken to minimize dis-

continuities on these transmission lines. Here are some

suggestions for maximizing the MAX3624A’s perfor-

mance:

• An uninterrupted ground plane should be posi-

tioned beneath the clock I/Os.

• Ground pin vias should be placed close to the IC

and the input/output interfaces to allow a return

current path to the MAX3624A and the receive

devices.

• Supply decoupling capacitors should be placed

close to the MAX3624A supply pins.

• Maintain 100

Ω differential (or 50Ω single-ended)

transmission line impedance out of the MAX3624A.

• Use good high-frequency layout techniques and a

multilayer board with an uninterrupted ground

plane to minimize EMI and crosstalk.

Refer to the MAX3624A Evaluation Kit for more information.

Exposed-Pad Package

The exposed pad on the 32-pin TQFN package pro-

vides a very low inductance path for return current trav-

eling to the PCB ground plane. The pad is also

electrical ground on the MAX3624A and must be sol-

dered to the circuit board ground for proper electrical

performance.

Chip Information

TRANSISTOR COUNT: 10,780

PROCESS: BiCMOS

Low-Jitter, Precision Clock Generator

with Four Outputs

______________________________________________________________________________________

11

10

Ω

10

Ω

ESD

STRUCTURES

QA_C

IN

DISABLE

Figure 9. Simplified LVCMOS Output Circuit Schematic

MAX3624A

THIN QFN

(5mm

TOP VIEW

5

6

4

3

20

19

21

22

910

SELB1

12

13

14

15

31

32

30

28

27

26

SELB0

QAC_OE

SELA1

SELA0

QA_OE

GND

11

29

7

18

MR

8

17

GNDO_A

QB0_OE

2

23

QB1_OE

GND

1

24

GND

16

25

+

*EP

*EXPOSED PAD CONNECTED TO GROUND.

Pin Configuration