bq24747

ELECTRICAL CHARACTERISTICS (continued)

7.0 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDSMB INPUT SUPPLY FOR SMBus

VDDSMB input voltage range

2.7

5.5

V

VDDSMB undervoltage lockout threshold

2.4

2.5

2.65

V

Threshold_Rising

voltage, rising

VDDSMB undervoltage lockout hysteresis

100

150

200

mV

Hyst_Rising

voltage, falling

IVDDSMB_Iq

VDDSMB quiescent current

20

27

μA

0°C

ELECTRICAL CHARACTERISTICS

7 Vdc

(1)

PARAMETER

MIN

TYP

MAX

UNIT

[SMB TIMING SPECIFICATION (VDD = 2.7 V to 5.5 V) (see Figures 4 and 5)]

SMBus TIMING CHARACTERISTICS

SCLK/SDATA rise time

1

μs

SCLK/SDATA fall time

300

ns

SCLK pulse width high

4

50

μs

SCLK Pulse Width Low

4.7

μs

Setup time for START condition

4.7

μs

START condition hold time after which first clock pulse is generated

4

μs

Data setup time

250

ns

Data hold time

300

ns

Setup time for STOP condition

4

μs

Bus free time between START and STOP condition

4.7

μs

Clock Frequency

10

100

kHz

HOST COMMUNICATION FAILURE

SMBus bus release timeout

22

25

35

ms

Watchdog timeout period

140

170

210

s

OUTPUT BUFFER CHARACTERISTICS

0.4

V

(1)

Devices participating in a transfer will timeout when any clock low exceeds the 25 ms minimum timeout period. Devices that have

detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave

must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a

slave (25 ms).

Copyright © 2009, Texas Instruments Incorporated

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