0V

SinkHotPlugDetect

Timeout

0V

Active

t T(HPD)

Standby

HPD _SRC

HPD_SINK

0V

tPD(CAD)

CAD _ SINK

CAD_ SRC

50%

50%

tPD(CAD)

0V

SN75DP120

www.ti.com

SLLSE08 – OCTOBER 2009

Figure 4. HPD Timing Diagram #2 (HPD_INV = L)

Figure 5. CAD Timing Diagram

DisplayPort Auxiliary Pins

The SN75DP120 is designed to monitor the bidirectional auxiliary signals in DP mode and participates in link

training. The SN75DP120 adjusts the output swing, output pre-emphasis, and the EQ setting of every main link

port. The SN75DP120 AUX monitor configures the output based on the DPCD addresses below.

The AUX channel is monitored for the Display Port D3 standby command. Upon detecting the D3 command, the

SN75DP120 will go into a low power standby state with the AUX activity monitor remaining active.

Table 3. DPCD Lookup Table

ADDRESS

NAME

DESCRIPTION

00100h

LINK_BW_SET

Main Link Bandwidth Setting

Bits 7:0 = link bandwidth setting

● 06h = 1.62Gbps per lane (default)

● 0Ah = 2.7Gbps per lane

Note: Setting the register value in register 0100h to anything else but 0Ah puts the device into

1.62Gbps mode.

00101h

LANE_COUNT_SET

Determines the number of lanes to be enabled

Bits 4:0 = lane count

● 1h = one lane

● 2h = two lanes

● 4h = four lanes

Note: Any other register value in register 0101h bit 4:0 is invalid and disables all OUTx lanes until

the register value is changed back to a valid entry. Default all lanes are disabled.

Copyright © 2009, Texas Instruments Incorporated

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