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TPS54318RTER Datasheet(PDF) 2 Page - Texas Instruments |
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TPS54318RTER Datasheet(HTML) 2 Page - Texas Instruments |
2 / 36 page TPS54318 SLVS975 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TJ PACKAGE PART NUMBER (1) TPS54318RTET –40°C to 150°C 3 × 3 mm QFN TPS54318RTER (1) The RTE package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g., TPS54318RTER). ABSOLUTE MAXIMUM RATINGS VALUE UNIT VIN –0.3 to 7 V EN –0.3 to 7 BOOT PH + 8 VSENSE –0.3 to 3 Input voltage COMP –0.3 to 3 PWRGD –0.3 to 7 SS –0.3 to 3 RT/CLK –0.3 to 6 BOOT-PH 8 V Output voltage PH –0.6 to 7 PH 10 ns Transient –2 to 7 EN 100 μA Source current RT/CLK 100 μA COMP 100 μA Sink current PWRGD 10 mA SS 100 μA Electrostatic discharge (HBM) 2 kV Electrostatic discharge (CDM) 500 V Operating Junction temperature, TJ –40 to 150 °C Storage temperature, Tstg –65 to 150 °C PACKAGE DISSIPATION RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) THERMAL IMPEDANCE θJT THERMAL CHARACTERISTIC PACKAGE JUNCTION TO AMBIENT JUNCTION TO TOP RTE 37°C/W 1°C/W (1) Maximum power dissipation may be limited by overcurrent protection (2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information. (3) Test boards conditions: (a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes on the 2 internal layers and bottom layer (d) 4 thermal vias (10mil) located under the device package 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54318 |
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