Electronic Components Datasheet Search |
|
FM3135-GTR Datasheet(PDF) 4 Page - Ramtron International Corporation |
|
FM3135-GTR Datasheet(HTML) 4 Page - Ramtron International Corporation |
4 / 21 page FM3135 Integrated RTC/Alarm/FRAM & Embedded Crystal Rev. 1.2 Feb. 2009 Page 4 of 21 VBC bit (register 0Eh, bit 2) is set to a ‘1’, the VBAK pin will source approximately 80 µA until VBAK reaches VDD. This charges the capacitor to VDD without an external diode and resistor charger. There is a Fast Charge mode which is enabled by the FC bit (register 0Eh, bit 1). In this mode the trickle charger current is set to approximately 1 mA, allowing a large backup capacitor to charge more quickly. • In the case where no battery is used, the VBAK pin should be tied to VSS. ! ! ! ! Note: systems using lithium batteries should clear the VBC bit to 0 to prevent battery charging. The VBAK circuitry includes an internal 1 K Ω series resistor as a safety element. The trickle charger is UL Recognized. Figure 2. Real-Time Clock Core Block Diagram Calibration When the CAL bit in register 00h is set to ‘1’, the clock enters calibration mode. In calibration mode, the ACS output pin is dedicated to the calibration function and the power fail output is temporarily unavailable. Calibration operates by applying a digital correction to the counter based on the frequency error. In this mode, the ACS pin is driven with a 512 Hz (nominal) square wave. Any measured deviation from 512 Hz translates into a timekeeping error. The user converts the measured error in ppm and writes the appropriate correction value to the calibration register. The correction factors are listed in the table below. Positive ppm errors require a negative adjustment that removes pulses. Negative ppm errors require a positive correction that adds pulses. Positive ppm adjustments have the CALS (sign) bit set to ‘1’, whereas negative ppm adjustments have CALS = 0. After calibration, the clock will have a maximum error of ± 2.17 ppm or ± 0.09 minutes per month at the calibrated temperature. The calibration setting is battery-backed and must be reloaded should the backup source fail. It is accessed with bits CAL.4-0 in register 01h. This value only can be written when the CAL bit is set to a ‘1’. To exit the calibration mode, the user must clear the CAL bit to a ‘0’. When the CAL bit is ‘0’, the ACS pin will revert to another function as defined in Table 3. Control Bit Settings for ACS Pin. 32.768 kHz crystal Oscillator Clock Divider Update Logic 512 Hz or SW out W R Seconds 7 bits Minutes 7 bits Hours 6 bits Date 6 bits Months 5 bits Years 8 bits Days 3 bits User Interface Registers 1 Hz /OSCEN CF |
Similar Part No. - FM3135-GTR |
|
Similar Description - FM3135-GTR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |