ICS854S013

LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER

PRELIMINARY

IDT™ / ICS™ LVDS FANOUT BUFFER

4

ICS854S013BG REV. A FEBRUARY 26, 2008

All parameters measured at 500MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured from the output differential cross points.

NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Differential Output Voltage

360

mV

∆V

OD

50

mV

Offset Voltage

1.35

V

∆V

OS

50

mV

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

>3

GHz

Propagation Delay; NOTE 1

TBD

ps

tsk(o)

Output Skew; NOTE 2, 4

<25

ps

tsk(b)

Bank Skew; NOTE 3, 4

<50

ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

100MHz, Integration Range:

12kHz – 20MHz

0.15

Output Rise/Fall Time

20% to 80%

200

ps

odc

Output Duty Cycle

50

%