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ICS813252I-02 Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS813252I-02 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 22 page  IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 10 CS813252CKI-02 REV. A OCTOBER 22, 2008 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS813252I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCX, VCCA, and V CCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V CC pin and also shows that V CCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the V CCA pin. FIGURE 1. POWER SUPPLY FILTERING of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V CC /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS V_REF R1 1K C1 0.1u R2 1K Single Ended Clock Input CLKx nCLKx VCC VDD VDDX VDDA 3.3V 10 Ω 10 Ω 10µF .01µF .01µF 10µF .01µF |
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