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EM68B32DVKA Datasheet(PDF) 9 Page - Etron Technology, Inc. |
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EM68B32DVKA Datasheet(HTML) 9 Page - Etron Technology, Inc. |
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9 / 40 page  EtronTech EM68B32DVKA Etron Confidential 9 Rev. 1.0 Mar. 2009 Extended Mode Register Set (EMRS ) The Extended Mode Register is designed to support Partial Array Self Refresh and Driver Strength. The EMRS cycle is not mandatory, and the EMRS command needs to be issued only when either PASR or DS is used. The Extended Mode Register is written by asserting Low on CS , RAS , CAS , WE , and BA0 and High on BA1 (the device should have all banks idle with no bursts in progress prior to writing into the Extended Mode Register, and CKE should be High). Values stored in the register will be retained until the register is reprogrammed, the device enters Deep Power Down mode, or power is removed from the device. The state of address pins A0~A12 and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Extended Mode Register. Two clock cycles, tMRD, are required to complete the write operation in the Extended Mode Register. A0~A2 are used for Partial Array Self Refresh and A5~A6 are used for Driver Strength. An automatic Temperature Compensated Self Refresh function is included with a temperature sensor embedded into this device. A3~A4 are no longer used to control this function; any inputs applied to A3~A4 during EMRS are ignored. All the other address pins, A7~A12 and BA0, must be set to Low for proper EMRS operation. Refer to the tables below for specific codes. If the user does not write values to the Extended Mode Register, DS defaults to Full Strength; and PASR defaults to the Full Array. Table 6. Extend Mode Register Bitmap BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 1 0 0 0 0 0 DS 0 0 PASR Mode Register A6 A5 Drive Strength A2 A1 A0 Partial Array Self Refresh Coverage 0 0 Full Strength 0 0 0 Full Array (All Banks) 0 1 1/2 Strength 0 0 1 Half of Full Array (BA1=0) 1 0 1/4 Strength 0 1 0 Quarter of Full Array (BA1=BA0=0) 1 1 1/8 Strength 0 1 1 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved TEMPERATURE COMPENSATED SELF REFRESH In order to reduce power consumption, a Mobile DDR SDRAM includes the internal temperature sensor and other circuitry to control Self Refresh operation automatically according to two temperature ranges: max. 40 °C and max. 85°C Table 7. IDD6 Specifications and Conditions Self Refresh Current (IDD6) Temperature Range Full Array 1/2 of Full Array 1/4 of Full Array Unit Max. 40 °C 490 350 280 µA Max. 85 °C 700 460 340 µA PARTIAL ARRAY SELF REFRESH For further power savings during Self Refresh, the PASR feature allows the controller to select the amount of memory that will be refreshed during Self Refresh. The refresh options are all banks (banks 0, 1, 2 and 3); two banks (bank 0 and 1); and one bank (bank 0). Write and Read commands can still affect any bank during standard operations, but only the selected banks will be refreshed during Self Refresh. Data in unselected banks will be lost. |
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