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AT91RM9200-CJ-002 Datasheet(PDF) 33 Page - ATMEL Corporation

Part # AT91RM9200-CJ-002
Description  ARM920T-based Microcontroller
Download  701 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT91RM9200-CJ-002 Datasheet(HTML) 33 Page - ATMEL Corporation

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1768I–ATARM–09-Jul-09
AT91RM9200
11. ARM920T Processor Overview
11.1
Overview
The ARM920T cached processor is a member of the ARM9Thumb family of high-performance
32-bit system-on-a-chip processors. It provides a complete high performance CPU subsystem
including:
• ARM9TDMI RISC integer CPU
• 16-Kbyte instruction and 16-Kbyte data caches
• Instruction and data memory management units (MMUs)
• Write buffer
•AMBA
(Advanced Microprocessor Bus Architecture) bus interface
• Embedded Trace Macrocell (ETM) interface
The ARM9TDMI core within the ARM920T executes both the 32-bit ARM and 16-bit Thumb
instruction sets. The ARM9TDMI processor is a Harvard architecture device, implementing a
five-stage pipeline consisting of Fetch, Decode, Execute, Memory and Write stages.
The ARM920T processor incorporates two coprocessors:
• CP14 - Controls software access to the debug communication channel
• CP15 - System Control Processor, providing 16 additional registers that are used to configure
and control the caches, the MMU, protection system, clocking mode and other system
options
The main features of the ARM920T processor are:
• ARM9TDMI-based, ARM Architecture v4T
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• 5-Stage Pipeline Architecture
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory Access (M)
– Register Write (W)
• 16-Kbyte Data Cache, 16-Kbyte Instruction Cache
– Virtually-addressed 64-way Associative Cache
– 8 Words per Line
– Write-though and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Low-power CAM RAM Implementation
• Write Buffer
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain


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