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AT91RM9200-CJ-002 Datasheet(PDF) 43 Page - ATMEL Corporation

Part # AT91RM9200-CJ-002
Description  ARM920T-based Microcontroller
Download  701 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT91RM9200-CJ-002 Datasheet(HTML) 43 Page - ATMEL Corporation

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1768I–ATARM–09-Jul-09
AT91RM9200
11.5
Memory Management Unit (MMU)
The ARM920T processor implements an enhanced ARM architecture v4 MMU to provide trans-
lation and access permission checks for the instruction and data address ports of the
ARM9TDMI core. The MMU is controlled from a single set of two-level page tables stored in the
main memory, providing a single address and translation protection scheme. Independently,
instruction and data TLBs in the MMU can be locked and flushed.
11.5.1
Domain
A domain is a collection of sections and pages. The ARM920T supports 16 domains. Access to
the domains is controlled by the Domain Access Control register. For details, refer to “CP15
Register 3, Domain Access Control Register” on page 50.
11.5.2
MMU Faults
The MMU generates alignment faults, translation faults, domain faults and permission faults.
Alignment fault checking is not affected by whether the MMU is enabled or not.
The access controls of the MMU detect the conditions that produce these faults. If the fault is a
result of memory access, the MMU aborts the access and signals the fault to the CPU core.The
MMU stores the status and address fault in the FSR and FAR registers (only for faults generated
by data access).
The MMU does not store fault information about faults generated by an instruction fetch.
The memory system can abort during line fetches, memory accesses and translation table
access.
Table 11-5.
Mapping Details
Mapping Name
Mapping Size
Access Permission By
Subpage Size
Section
1M byte
Section
-
Large Page
64K bytes
4 separated subpages
16K bytes
Small Page
4K bytes
4 separated subpages
1K byte
Tiny Page
1K byte
Tiny Page
-


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