HANBit

HSD32M72D18R

URL:www.hbe.co.kr

HANBit Electronics Co.,Ltd

REV.1.0 (August.2002).

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

/CE

Chip enable

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+tss prior to valid command.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

/RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

/CAS

Column

address

strobe

Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

/WE

Write

enable

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

DQM0 ~ 7

Data

input/output

mask

Makes data output Hi-Z, tsHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

REGE

Register enable

The device operates in the transparent mode when REGE is low. When REGE is

high, the

device operates in the registered mode. In registered mode, the Address and

control inputs are latched if CLK is held at a high or low logic level. The inputs are

through 10K ohm register on PCB. So if REGE of module is floating, this module

will be operated as registerd mode.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

CB0~7

Check bit

Check bits for ECC.

WP

Write Protection

WP pin is connected to Vcc.

When WP is

“high”, EEPROM Programming will be inhibited and the entire

memory will be write-protected.

VDD/VSS

Power

supply/ground

Power and ground for the input buffers and the core logic.