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ISL80102IR15Z Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL80102IR15Z Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 16 page  7 FN6660.0 September 30, 2009 Application Section Input Voltage Requirements Despite other output voltages offered, this family of LDOs is optimized for a true 2.5V to 1.8V conversion where the input supply can have a tolerance of as much as ±10% for conditions noted in the “Electrical Specifications” table on page 5. Minimum guaranteed input voltage is 2.2V. However, due to the nature of an LDO, VIN must be some margin higher than the output voltage plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The Dropout spec of this family of LDOs has been generously specified in order to allow applications to design for a level of efficiency that can accommodate the smaller outline package for those applications that cannot accommodate the profile of the TO220/263. External Capacitor Requirements GENERAL GUIDELINE External capacitors are required for proper operation. Careful attention must be paid to layout guidelines and selection of capacitor type and value to ensure optimal performance. OUTPUT CAPACITOR The required minimum output capacitor is 10µF X5R/X7R to ensure stable operation. Lower cost Y5V and Z5U type ceramic capacitors are acceptable if the size of the capacitor is larger to compensate for the significantly lower tolerance over X5R/X7R types (approximately 2x). Additional capacitors of any value in Ceramic, POSCAP or Alum/Tantalum Electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. This minimum capacitor must be connected to VOUT and Ground pins of the LDO with PCB traces no longer than 0.5cm. INPUT CAPACITOR The minimum input capacitor required for proper operation is 10µF having a ceramic dielectric. This minimum capacitor must be connected to VOUT and Ground pins of the LDO with PCB traces no longer than 0.5cm. Thermal Fault Protection In the event the die temperature exceeds typically +160°C, then the output of the LDO will shut down until the die temperature can cool down to typically +145°C. The level of power combined with the thermal impedance of the package (+50°C/W for DFN) will determine if the junction temperature exceeds the thermal shutdown temperature specified in the “Electrical Specifications” table on page 5 (see thermal packaging guidelines). Current Limit Protection The ISL80102/3 family of LDOs incorporates protection against overcurrent due to any short or overload condition applied to the output pin. The current limit circuit performs as a constant current source when the output current exceeds the current limit threshold noted in the “Electrical Specifications” table on page 5. If the short or overload condition is removed from VOUT, then the output returns to normal voltage mode regulation. In the event of an overload condition on the DFN package the LDO will begin to cycle on and off due to the die temperature exceeding thermal fault condition. The TO220/263 package will tolerate higher levels of power dissipation on the die which may never thermal cycle if the heatsink of this larger package can keep the die temperature below the specified typical thermal shutdown temperature. Functional Description Enable Operation The Enable turn-on threshold is typically 770mV with a hysteresis of 135mV. The Enable pin doesn't have an internal pull-up or pull-down resistor. As a result, this pin must not be left floating. This pin must be tied to VIN if it is not used. A 1kΩ to 10kΩ pull-up resistor will be required for applications that use open collector or open drain outputs to control the Enable pin. The Enable pin may be connected directly to VIN for applications that are always on. Soft-Start Operation The soft start circuit controls the rate at which the output voltage comes up to regulation at power-up or coming out of a chip disable. A constant current charges an external soft start capacitor. The external capacitor always gets discharged to 0V at start-up of after coming out of a chip disable. The discharge rate is the RC time constant of RPD and CSS. The soft-start function effectively limits the amount of in-rush current below the programmed current limit during start-up or an enable sequence to avoid an overcurrent fault condition. This can be an issue for applications that require large, external bulk capacitances on VOUT where high levels of charging current can be seen for a significant period of time. High in-rush currents can cause VIN to drop below minimum which could cause VOUT to shutdown. Figure 3 shows the relationship between in-rush current and CSS with a COUT of 1000µF. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 204060 80 100 Css (nF) FIGURE 3. IN-RUSH CURRENT vs SOFT-START CAPACITANCE ISL80102, ISL80103 |
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