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NCP5380MNR2G Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP5380MNR2G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 27 page NCP5380 http://onsemi.com 8 Pin Function Descriptions Pin No. Mnemonic Description 1 PWRGD Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the VID DAC defined range. 2 IMON Current Monitor Output. This pin sources current proportional to the output load current. A resistor connec- ted to VSS Sense sets the current monitor gain. 3 N/C 4 FBRTN Feedback Return Input/Output. This pin remotely senses the output voltage. It is also used as the ground return for the VID DAC and the voltage error amplifier blocks. It is also used to adjust the no−load offset. 5 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier. 6 COMP Voltage Error Amplifier Output and Frequency Compensation Point. 7 GND Analog and digital signal ground. 8 ILIM Current Limit Set pin. Connect a resistor between ILIM and CSCOMP to the current limit threshold. 9 IREF This pin sets the internal bias currents. A 100 kW is connected from IREF to ground. 10 RPM RPM Mode Timing Control Input. A resistor is connected from RPM to ground sets the RPM mode turn−on threshold voltage. 11 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator frequency. 12 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets the slope of the internal PWM stabilizing ramp. 13 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF and CSCOMP tied to this pin sets the load line slope. 14 CSREF Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor. 15 CSFB Noninverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node to this pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current sense amplifier. 16 CSCOMP Current Sense Amplifier Output. 17 GND Analog and Digital Signal Ground. 18 PGND Low−Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s). 19 DRVL Low−Side Gate Drive Output. 20 PVCC Power Supply Input/Output of Low−Side Gate Driver. 21 SW Current Return For High−Side Gate Drive. 22 DRVH High−Side Gate Drive Output. 23 BST High−Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the high−side MOSFET is on. 24 VCC Power Supply Input/Output of the Controller. 25 to 31 VID7 to VID1 Voltage Identification DAC Inputs. A 7−bit word (the VID code) programs the DAC output voltage, the refer- ence voltage of the voltage error amplifier without a load (see the VID code table, Table 4). In normal opera- tion mode, the VID DAC output programs the output voltage to a value within the 0 V to 1.6 V range (with FBRTN = 112.5 mV). The input is actively pulled down. 32 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low. Flag PGND High current power supply return via metal pad (flag) underneath package. Connect to pin 7. |
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