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AD7298 Datasheet(PDF) 4 Page - Analog Devices |
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AD7298 Datasheet(HTML) 4 Page - Analog Devices |
4 / 18 page Preliminary Technical Data AD7298 Rev. PrA | Page 4 of 18 TIMING SPECIFICATIONS VDD = 2.8V to 3.6V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal/external; TA = −40°C to + 125°C, unless otherwise noted. 7 Table 3. Parameter Limit at T MIN, TMAX Unit Test Conditions/Comments tCONVERT 16 × tSCLK µs max Conversion time 1 µs max For each ADC channel VIN0 to VIN7, FSCLK = 20MHz 100 µs max For Temperature Sensor channel fSCLK 50 kHz min Frequency of external serial clock 20 MHz max Frequency of external serial clock tQUIET TBD ns min Minimum quiet time required between the end of serial read and the start of the next voltage conversion in repeat and non-repeat mode. TBD ns min Minimum quiet time required between the end of serial read and the start of the next temperature conversion, for consecutive Temperature conversions. t2 10 ns min CS to SCLK setup time t3 25 ns max Delay from CS until DOUT three-state disabled t4 TBD ns max Data access time after SCLK falling edge t5 0.4 × tSCLK ns min SCLK low pulsewidth t6 0.4 × tSCLK ns min SCLK high pulsewidth t7 TBD ns min SCLK to DOUT valid hold time t8 15/45 ns min/max SCLK falling edge to DOUT high impedance t9 10 ns min DIN setup time prior to SCLK falling edge t10 5 ns min DIN hold time after SCLK falling edge t11 TBD ns min TSENSEBUSY falling edge to CS falling edge tPOWER- UP_PARTIAL TBD μs max Power-up time from partial power-down tPOWER-UP TBD μs max Power-up time from full power-down 7 Sample tested during initial release to ensure compliance. All input signals are specified with t R = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. |
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