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ADP5022ACBZ-1-R7 Datasheet(PDF) 6 Page - Analog Devices |
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ADP5022ACBZ-1-R7 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 28 page  ADP5022 Rev. A | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating VDDA, VIN1, VIN2, VIN3, VOUT1, VOUT2, VOUT3, EN1, EN2, EN3, MODE to GND −0.3 V to +6 V Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP5022 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature (TA) does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature may exceed the maximum limit as long as the junction temperature is within specification limits. TJ of the device is dependent on TA, the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance (θJA) of the package. Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD × θJA) θJA of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and envi- ronmental conditions. The specified values of θJA are based on a 4-layer, 4” × 3” circuit board. Refer to JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered on a circuit board. Table 5. Thermal Resistance Package Type θJA Unit 16-Ball, 0.5 mm Pitch WLCSP 65 °C/W ESD CAUTION |
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