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73K224L Datasheet(PDF) 5 Page - Teridian Semiconductor Corporation |
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73K224L Datasheet(HTML) 5 Page - Teridian Semiconductor Corporation |
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5 / 31 page  73K224L V.22bis, V.22, V.21, Bell 212A, 103 Single-Chip Modem DATA SHEET Page: 5 of 31 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 DTE USER INTERFACE NAME TYPE DESCRIPTION EXCLK I External Clock. This signal is used in synchronous transmission when the external timing option has been selected. In the external timing mode the rising edge of EXCLK is used to strobe synchronous transmit data available on the TXD pin. Also used for serial control interface. RXCLK O/ Tristate Receive Clock. Tri stateable. The falling edge of this clock output is coincident with the transitions in the serial received data output. The rising edge of RXCLK can be used to latch QAM or DPSK valid output data. RXCLK will be active as long as a carrier is present. RXD O/ Weak Pull-up Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected. TXCLK O/ Tristate Transmit Clock. Tri stateable. This signal is used in synchronous transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the synchronization mode selection. In Internal Mode the clock is generated internally. In External Mode TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin. TXCLK is always active. TXD I Transmit Digital Data Input. Serial data for transmission is input on this pin. In synchronous modes, the data must be valid on the rising edge of the TXCLK clock. In asynchronous modes (2400/1200/600 bit/s or 300 baud) no clocking is necessary. DPSK data must be +1%, -2.5% or +2.3%, -2.5 % in extended overspeed mode. ANALOG INTERFACE AND OSCILLATOR RXA I Received modulated analog signal input from the phone line. TXA O Transmit analog output to the phone line. XTL1 I These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel mode crystal. Two capacitors from these pins to ground are also required for proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock. XTL2 I/O |
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