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73K324BL Datasheet(PDF) 11 Page - Teridian Semiconductor Corporation |
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73K324BL Datasheet(HTML) 11 Page - Teridian Semiconductor Corporation |
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11 / 34 page  73K324BL CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem w/ Integrated Hybrid DATA SHEET Page: 11 of 34 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 6.1 CONTROL REGISTER 0 D7 D6 D5 D4 D3 D2 D1 D0 CR0 000 MODUL. OPTION MODUL. TYPE 1 MODUL. TYPE 0 TRANSMIT MODE 2 TRANSMIT MODE 1 TRANSMIT MODE 0 TRANSMIT ENABLE ANSWER/ ORIGINATE BIT NAME CONDITION DESCRIPTION D0 Answer/ 0 Selects answer mode (transmit in high band, receive Originate in low band) or in V.23 HDX mode, receive at 1200 bps and transmit at 75 bps. 1 Selects originate mode (transmit in low band, receive in high band) or in V.23 HDX mode, receive at 1200 bps and transmit at 75 bps. Note: This bit works with Tone Register bits D0 and D6 to program special tones detected in the Detect Register. See Detect and Tone Registers. D1 Transmit 0 Disables transmit output at TXA1 & TXA2 Enable 1 Enables transmit output at TXA1 & TXA2 Note: Transmit enable must be set to 1 to allow activation of answer tone or DTMF. D5,D4 Transmit D5 D4 D3 D2 D3,D2 Mode 0 0 0 0 Selects Power down mode. All functions disabled except digital interface. 0 0 0 1 Internal synchronous mode in this mode TXCLK is an internally derived 600,1200 or 2400 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. 0 0 1 0 External synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be supplied externally. 0 0 1 1 Slave synchronous mode Same operation as other synchronous modes TXCLK is connected internally to the RXCLK pin in this mode. 0 1 0 0 Selects a synchronous mode 8 bits/character (1 start bit, 6 data bits, 1 stop bit). 0 1 0 1 Selects asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). 0 1 1 0 Selects asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). 0 1 1 1 Selects asynchronous mode - 11 bits/character (1 start bit, 8 data bits, 1 stop bit) or 2 stop bits).. 1 X 0 0 Selects FSK operation. |
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