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73K324L Datasheet(PDF) 5 Page - Teridian Semiconductor Corporation |
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73K324L Datasheet(HTML) 5 Page - Teridian Semiconductor Corporation |
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5 / 30 page  73K324L CCITT V.22bis,V.23,V.22,V.21, Bell 212A Single-Chip Modem DATA SHEET Page: 5 of 30 © 2005, 2008 TERIDIAN Semiconductor Corporation Rev 7.1 RS-232 INTERFACE NAME TYPE DESCRIPTION EXCLK I External Clock. This signal is used in synchronous transmission when the external timing option has been selected. In the External Timing mode the rising edge of EXCLK is used to strobe synchronous transmit data available on the TXD pin. Also used for serial control interface. RXCLK O/Tristate Receive Clock Tri-statable. The falling edge of this clock output is coincident with the transitions in the serial received DPSK/QAM data output. The rising edge of RXCLK can be used to latch the valid output data. RXCLK will be valid as long as a carrier is present. In V.23 or V.21 mode a clock that is 16 x 1200/75 or 16 x 300 Hz data rate is output, respectively. RXD O/ Weak Pull-up Received Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in Synchronous mode. RXD will output constant marks if no carrier is detected. TXCLK O/Tristate Transmit Clock Tri-statable. This signal is used in synchronous DPSK/QAM transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the Synchronization mode selection. In Internal Mode the clock is generated internally (2400 Hz for QAM, 1200 Hz for DPSK or 600 Hz for half-speed DPSK). In External Mode TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin. TXCLK is always active. In V.23 or V.21 mode the output is a 16 x 1200/75 or 16 x 300 Hz clock, respectively. TXD I Transmit Data Input. Serial data for transmission is input on this pin. In Synchronous modes, the data must be valid on the rising edge of the TXCLK clock. In Asynchronous modes (2400/1200/600 bit/s, or 75/300 baud) no clocking is necessary. DPSK/QAM data must be +1%, -2.5% or +2.3%, -2.5 % in Extended Overspeed mode. ANALOG INTERFACE RXA I Received modulated analog signal input from the phone line. TXA O Transmit analog output to the phone line. XTL1 I These pins are for the internal crystal oscillator requiring a 11.0592 MHz Parallel mode crystal. Two capacitors from these pins to ground are also required for proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock. XTL2 I/O |
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