73S8010R

Low Cost Smart Card Interface

DATA SHEET

Page: 6 of 24

Rev 1.5

I

I

address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode bit

(R/

W) – a ‘zero’ indicates the master will write data to the control register. After the R/W bit, the ’zero’ ACK bit is

sent to the master by the device. The master now starts sending the 8 bits of data to the control register during

the DATA bits. After the DATA bits, the ‘zero’ ACK bit is sent to the master by the device. The master should send

the STOP condition after receiving this ACK bit.

1-78

91-8

9

ADDRESSbits

R/

W bit

ACKbit

DATAbits

ACKbit

STOP

condition

START

condition

SCL

SDA

MSB

MSB

LSB

LSB

Figure 2 - I

STATUS register

Power On Reset = 04h

Name

Bit

Description

PRES

0

Set when the card is present (pin PRES is high); reset when the card is

not present.

PRESL

1

Set when the PRES pin changes state (rising/falling edge); reset when

the status register is read. Generates an interrupt when set.

I/O

2

Set when I/O is high; reset when I/O is low.

SUPL

3

Set when a voltage fault is detected; reset when the status register is

read. Generates an interrupt when set

PROT

4

Set when an over-current or over-heating fault has occurred during a

card session; reset when the status register is read. Generates an

interrupt when set

MUTE

5

Set during ATR when the card has not answered during the ISO 7816-3

time window (40000 card clock cycles); reset when the next session

begins.

EARLY

6

Set during ATR when the card has answered before 400 card clock

cycles; reset when the next session begin.

ACTIVE

7