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HT56R64 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT56R64 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 90 page  HT56R64 Rev. 1.40 9 September 8, 2009 System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their in- ternal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, in- crement, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accu- mulator and the ALU. Certain internal registers are im- plemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural fea- tures ensure that a minimum of external components is required to provide a functional I/O and A/D control sys- tem with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a Crys- tal/Resonator or RC oscillator is subdivided into four in- ternally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive in- struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is free for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to com- plete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. F e t c h I n s t . ( P C ) E x e c u t e I n s t . ( P C - 1 ) F e t c h I n s t . ( P C + 1 ) E x e c u t e I n s t . ( P C ) F e t c h I n s t . ( P C + 2 ) E x e c u t e I n s t . ( P C + 1 ) P C P C + 1 P C + 2 O s c i l l a t o r C l o c k ( S y s t e m C l o c k ) P h a s e C l o c k T 1 P r o g r a m C o u n t e r P h a s e C l o c k T 2 P h a s e C l o c k T 3 P h a s e C l o c k T 4 P i p e l i n i n g System Clocking and Pipelining F e t c h I n s t . 1 E x e c u t e I n s t . 1 F e t c h I n s t . 2 F l u s h P i p e l i n e 1 2 3 4 5 6 D E L A Y : M O V A , [ 1 2 H ] C A L L D E L A Y C P L [ 1 2 H ] : : N O P E x e c u t e I n s t . 2 F e t c h I n s t . 3 F e t c h I n s t . 6 E x e c u t e I n s t . 6 F e t c h I n s t . 7 Instruction Fetching |
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