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HT82D22A Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT82D22A Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 41 page  HT82D22R/HT82D22A Rev. 1.00 11 November 6, 2009 other registers. Any data written into the status register will not change the TO or PDF flag. In addition, opera- tions related to the status register may give different re- sults from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by exe- cuting the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or exe- cuting a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter- rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be pre- vented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC) will be set. · Access of the corresponding USB FIFO from PC · The USB suspend signal from PC · The USB resume signal from PC · USB Reset signal When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca- tion 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO, the corresponding request bit of the USR is set, and a USB interrupt is trig- gered. So user can easily decide which FIFO is ac- cessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the device receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) is set and a USB interrupt is also triggered. When the device receives a Resume signal from the Host PC, the resume line (bit3 of the USC) are set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB in- terrupt is triggered and URST bit of the USC register is set. When the interrupt has been served, the bit should be cleared by firmware. The internal Timer/Event Counter 0 interrupt is initial- ized by setting the Timer/Event Counter 0 interrupt re- quest flag (T0F; bit 5 of INTC), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further in- terrupts. The internal Timer/Even Counter 1 interrupt is initialized Bit No. Label Function 0 EMI Controls the master (global) interrupt (1=enable; 0=disable) 1 EUI Controls the USB interrupt (1=enable; 0= disable) 2 ET0I Controls the Timer/Event Counter0 interrupt (1=enable; 0=disable) 3 ET1I Controls the Timer/Event Counter1 interrupt (1=enable; 0=disable) 4 USBF USB interrupt request flag (1=active; 0=inactive) 5 T0F Internal Timer/Event counter0 request flag (1:active; 0:inactive) 6 T1F Internal timer/event counter request flag (1:active; 0:inactive) 7 ¾ Unused bit, read as ²0² INTC (0BH) Register |
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