Timing Diagram

Note:

The output is activated if the trigger signal conforms to the following criteria:

· More than 3 triggers within 2 seconds

· A trigger signal sustain duration ³ 0.34 secs

· 2 trigger signals within 2 secs with one of the trigger signal sustain ³ 0.16 secs.

The effective comparator output width can be selected to be 24ms or 32ms or 48ms by mask option.

The default is 24ms (system frequency=16kHz).

The output duration is set by an external RC that is connected to the OSCD pin.

HT761X

Rev. 1.30

7

October 12, 2009

Fig.4 and Fig.5 are similar but in Fig.5 the input signal of

amplifier is taken from the drain of the PIR. This has

higher gain than that in Fig.4. Since OP1 is a PMOS in-

put VD, it has to be greater than 1.2V for adequate oper-

ation.

D

G

S

P I R

5 6 k W

O P 1

O P 1 O U T

V E E

V E E

C 1

2 2 m F

R 1

2 2 k W

R 2

1 M W

C 2

0 . 0 2 2 m F

Fig. 4 Typical First-Stage PIR

D

G

S

P I R

O P 1

O P 1 O U T

V E E

C 1 5

1 0 0 m F

R 4

5 6 k W

V E E

R 1 2

5 1 0 k W

R 1 1

2 2 k W

C 1 1

2 2 m F

R 1 3

1 0 0 k W ~ 1 8 0 k W

C 1 2

0 . 0 4 7

Fig.5 High Gain First Stage

5 s e c

+ t r i g g e r l e v e l

< 2 4 m s

> 2 4 m s

( N o t e 1 )

- t r i g g e r l e v e l

p o w e r - o n d e l a y t i m e

O N

R S T

C D S

O u t p u t

E n a b l e

C o m p a r a t o r

I n p u t

C o m p a r a t o r

o u t p u t

D e t e c t

E n a b l e

O N

R E L A Y

T R I A C

T e s t E n a b l e

1 0 S

t e s t e n a b l e

4 0 S

( N o t e 2 )

p u l s e o u t p u t

( N o t e 3 )